Wafer-lever hermetic package with through-wafer interconnects

This paper reports a new wafer-level hermetic packaging structure with the features of low processing cost and high I/O density by using wet and dry sequentially etched through-wafer vias for the interconnects of a microelectro mechanical systems (MEMS) device. A thin Si wafer cap and wafer-level fa...

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Bibliographic Details
Published in:Journal of electronic materials 2007-02, Vol.36 (2), p.105-109
Main Authors: WANG, Yu-Churn, ZHU, Da-Peng, XU WEI, LE LUO
Format: Article
Language:English
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Etching and cleaning
Exact sciences and technology
Integrated circuits
Interconnect
Micro- and nanoelectromechanical devices (mems/nems)
Microelectromechanical systems
Microelectronic fabrication (materials and surfaces technology)
Physics
Physics of gases, plasmas and electric discharges
Physics of plasmas and electric discharges
Plasma applications
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon wafers
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Summary:This paper reports a new wafer-level hermetic packaging structure with the features of low processing cost and high I/O density by using wet and dry sequentially etched through-wafer vias for the interconnects of a microelectro mechanical systems (MEMS) device. A thin Si wafer cap and wafer-level fabrication processes such as deep reactive ion etching (DRIE) and KOH etching, bottom-up copper filling, and Sn solder bonding were adopted. The hermeticity and bonding strength of the structure are evaluated. Preliminary results show that the hermeticity can meet the requirement of the criterion of MIL-STD 883E, method 1014.9, and the bonding strength is up to 8 MPa. [PUBLICATION ABSTRACT]
ISSN:0361-5235
1543-186X
DOI:10.1007/s11664-006-0016-1