Loading…
Increased Rate of Multiple-Bit Upset From Neutrons at Large Angles of Incidence
Neutron interactions with terrestrial systems produce soft errors, increasing the failure-in-time (FIT) rate of advanced CMOS circuits. These neutron-induced errors are a critical reliability problem facing advanced technologies. This paper reports the accelerated neutron testing on a 90-nm CMOS SRA...
Saved in:
Published in: | IEEE transactions on device and materials reliability 2008-09, Vol.8 (3), p.565-570 |
---|---|
Main Authors: | , , , , , , , , |
Format: | Magazinearticle |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | cdi_FETCH-LOGICAL-c421t-a4cefdb7d72be1d8ee603096dada83afb4197bb15408d427ce611c832c90e9573 |
---|---|
cites | cdi_FETCH-LOGICAL-c421t-a4cefdb7d72be1d8ee603096dada83afb4197bb15408d427ce611c832c90e9573 |
container_end_page | 570 |
container_issue | 3 |
container_start_page | 565 |
container_title | IEEE transactions on device and materials reliability |
container_volume | 8 |
creator | Tipton, A.D. Xiaowei Zhu Haixiao Weng Pellish, J.A. Fleming, P.R. Schrimpf, R.D. Reed, R.A. Weller, R.A. Mendenhall, M. |
description | Neutron interactions with terrestrial systems produce soft errors, increasing the failure-in-time (FIT) rate of advanced CMOS circuits. These neutron-induced errors are a critical reliability problem facing advanced technologies. This paper reports the accelerated neutron testing on a 90-nm CMOS SRAM that exhibits an increased multiple-bit upset FIT rate from neutrons at large angles of incidence. The modeling of these data is used to predict the reliability of ground-based systems. |
doi_str_mv | 10.1109/TDMR.2008.2002356 |
format | magazinearticle |
fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_36331142</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4655571</ieee_id><sourcerecordid>36331142</sourcerecordid><originalsourceid>FETCH-LOGICAL-c421t-a4cefdb7d72be1d8ee603096dada83afb4197bb15408d427ce611c832c90e9573</originalsourceid><addsrcrecordid>eNp9kT1PwzAQhiMEEqXwAxCLxQBTwN9xxlIoVGqpVLWz5diXKlWaBDsZ-PckasXAwHJ3w_Oe7vRE0S3BT4Tg9Hnzulw_UYzVUCgT8iwaESFUTEXCz4eZ4ZgzpS6jqxD2GJM0EXIUreaV9WACOLQ2LaA6R8uubIumhPilaNG2CdCima8P6BO61tdVQKZFC-N3gCbVroQwZPothYPKwnV0kZsywM2pj6Pt7G0z_YgXq_f5dLKILaekjQ23kLsscQnNgDgFIDHDqXTGGcVMnvH-viwjgmPlOE0sSEKsYtSmGFKRsHH0eNzb-Pqrg9DqQxEslKWpoO6CVonAElPOe_LhX5JJxgjhtAfv_4D7uvNV_4VOCaUKY5H2EDlC1tcheMh144uD8d-aYD2Y0IMJPZjQJxN95u6YKQDgl-dSCJEQ9gPBNoMO</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>magazinearticle</recordtype><pqid>912280059</pqid></control><display><type>magazinearticle</type><title>Increased Rate of Multiple-Bit Upset From Neutrons at Large Angles of Incidence</title><source>IEEE Xplore (Online service)</source><creator>Tipton, A.D. ; Xiaowei Zhu ; Haixiao Weng ; Pellish, J.A. ; Fleming, P.R. ; Schrimpf, R.D. ; Reed, R.A. ; Weller, R.A. ; Mendenhall, M.</creator><creatorcontrib>Tipton, A.D. ; Xiaowei Zhu ; Haixiao Weng ; Pellish, J.A. ; Fleming, P.R. ; Schrimpf, R.D. ; Reed, R.A. ; Weller, R.A. ; Mendenhall, M.</creatorcontrib><description>Neutron interactions with terrestrial systems produce soft errors, increasing the failure-in-time (FIT) rate of advanced CMOS circuits. These neutron-induced errors are a critical reliability problem facing advanced technologies. This paper reports the accelerated neutron testing on a 90-nm CMOS SRAM that exhibits an increased multiple-bit upset FIT rate from neutrons at large angles of incidence. The modeling of these data is used to predict the reliability of ground-based systems.</description><identifier>ISSN: 1530-4388</identifier><identifier>EISSN: 1558-2574</identifier><identifier>DOI: 10.1109/TDMR.2008.2002356</identifier><identifier>CODEN: ITDMA2</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Accelerated tests ; Angle of incidence ; Circuit testing ; Circuits ; CMOS ; CMOS technology ; Devices ; Error correction ; Incidence ; Life estimation ; Mathematical models ; Multiple-bit upset (MBU) ; NASA ; neutron ; Neutrons ; Predictive models ; Protons ; Random access memory ; Semiconductor device modeling ; soft error ; Soft errors</subject><ispartof>IEEE transactions on device and materials reliability, 2008-09, Vol.8 (3), p.565-570</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2008</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c421t-a4cefdb7d72be1d8ee603096dada83afb4197bb15408d427ce611c832c90e9573</citedby><cites>FETCH-LOGICAL-c421t-a4cefdb7d72be1d8ee603096dada83afb4197bb15408d427ce611c832c90e9573</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4655571$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>776,780,27904,54775</link.rule.ids></links><search><creatorcontrib>Tipton, A.D.</creatorcontrib><creatorcontrib>Xiaowei Zhu</creatorcontrib><creatorcontrib>Haixiao Weng</creatorcontrib><creatorcontrib>Pellish, J.A.</creatorcontrib><creatorcontrib>Fleming, P.R.</creatorcontrib><creatorcontrib>Schrimpf, R.D.</creatorcontrib><creatorcontrib>Reed, R.A.</creatorcontrib><creatorcontrib>Weller, R.A.</creatorcontrib><creatorcontrib>Mendenhall, M.</creatorcontrib><title>Increased Rate of Multiple-Bit Upset From Neutrons at Large Angles of Incidence</title><title>IEEE transactions on device and materials reliability</title><addtitle>TDMR</addtitle><description>Neutron interactions with terrestrial systems produce soft errors, increasing the failure-in-time (FIT) rate of advanced CMOS circuits. These neutron-induced errors are a critical reliability problem facing advanced technologies. This paper reports the accelerated neutron testing on a 90-nm CMOS SRAM that exhibits an increased multiple-bit upset FIT rate from neutrons at large angles of incidence. The modeling of these data is used to predict the reliability of ground-based systems.</description><subject>Accelerated tests</subject><subject>Angle of incidence</subject><subject>Circuit testing</subject><subject>Circuits</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>Devices</subject><subject>Error correction</subject><subject>Incidence</subject><subject>Life estimation</subject><subject>Mathematical models</subject><subject>Multiple-bit upset (MBU)</subject><subject>NASA</subject><subject>neutron</subject><subject>Neutrons</subject><subject>Predictive models</subject><subject>Protons</subject><subject>Random access memory</subject><subject>Semiconductor device modeling</subject><subject>soft error</subject><subject>Soft errors</subject><issn>1530-4388</issn><issn>1558-2574</issn><fulltext>true</fulltext><rsrctype>magazinearticle</rsrctype><creationdate>2008</creationdate><recordtype>magazinearticle</recordtype><recordid>eNp9kT1PwzAQhiMEEqXwAxCLxQBTwN9xxlIoVGqpVLWz5diXKlWaBDsZ-PckasXAwHJ3w_Oe7vRE0S3BT4Tg9Hnzulw_UYzVUCgT8iwaESFUTEXCz4eZ4ZgzpS6jqxD2GJM0EXIUreaV9WACOLQ2LaA6R8uubIumhPilaNG2CdCima8P6BO61tdVQKZFC-N3gCbVroQwZPothYPKwnV0kZsywM2pj6Pt7G0z_YgXq_f5dLKILaekjQ23kLsscQnNgDgFIDHDqXTGGcVMnvH-viwjgmPlOE0sSEKsYtSmGFKRsHH0eNzb-Pqrg9DqQxEslKWpoO6CVonAElPOe_LhX5JJxgjhtAfv_4D7uvNV_4VOCaUKY5H2EDlC1tcheMh144uD8d-aYD2Y0IMJPZjQJxN95u6YKQDgl-dSCJEQ9gPBNoMO</recordid><startdate>20080901</startdate><enddate>20080901</enddate><creator>Tipton, A.D.</creator><creator>Xiaowei Zhu</creator><creator>Haixiao Weng</creator><creator>Pellish, J.A.</creator><creator>Fleming, P.R.</creator><creator>Schrimpf, R.D.</creator><creator>Reed, R.A.</creator><creator>Weller, R.A.</creator><creator>Mendenhall, M.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20080901</creationdate><title>Increased Rate of Multiple-Bit Upset From Neutrons at Large Angles of Incidence</title><author>Tipton, A.D. ; Xiaowei Zhu ; Haixiao Weng ; Pellish, J.A. ; Fleming, P.R. ; Schrimpf, R.D. ; Reed, R.A. ; Weller, R.A. ; Mendenhall, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c421t-a4cefdb7d72be1d8ee603096dada83afb4197bb15408d427ce611c832c90e9573</frbrgroupid><rsrctype>magazinearticle</rsrctype><prefilter>magazinearticle</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Accelerated tests</topic><topic>Angle of incidence</topic><topic>Circuit testing</topic><topic>Circuits</topic><topic>CMOS</topic><topic>CMOS technology</topic><topic>Devices</topic><topic>Error correction</topic><topic>Incidence</topic><topic>Life estimation</topic><topic>Mathematical models</topic><topic>Multiple-bit upset (MBU)</topic><topic>NASA</topic><topic>neutron</topic><topic>Neutrons</topic><topic>Predictive models</topic><topic>Protons</topic><topic>Random access memory</topic><topic>Semiconductor device modeling</topic><topic>soft error</topic><topic>Soft errors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Tipton, A.D.</creatorcontrib><creatorcontrib>Xiaowei Zhu</creatorcontrib><creatorcontrib>Haixiao Weng</creatorcontrib><creatorcontrib>Pellish, J.A.</creatorcontrib><creatorcontrib>Fleming, P.R.</creatorcontrib><creatorcontrib>Schrimpf, R.D.</creatorcontrib><creatorcontrib>Reed, R.A.</creatorcontrib><creatorcontrib>Weller, R.A.</creatorcontrib><creatorcontrib>Mendenhall, M.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE/IET Electronic Library</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on device and materials reliability</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Tipton, A.D.</au><au>Xiaowei Zhu</au><au>Haixiao Weng</au><au>Pellish, J.A.</au><au>Fleming, P.R.</au><au>Schrimpf, R.D.</au><au>Reed, R.A.</au><au>Weller, R.A.</au><au>Mendenhall, M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Increased Rate of Multiple-Bit Upset From Neutrons at Large Angles of Incidence</atitle><jtitle>IEEE transactions on device and materials reliability</jtitle><stitle>TDMR</stitle><date>2008-09-01</date><risdate>2008</risdate><volume>8</volume><issue>3</issue><spage>565</spage><epage>570</epage><pages>565-570</pages><issn>1530-4388</issn><eissn>1558-2574</eissn><coden>ITDMA2</coden><abstract>Neutron interactions with terrestrial systems produce soft errors, increasing the failure-in-time (FIT) rate of advanced CMOS circuits. These neutron-induced errors are a critical reliability problem facing advanced technologies. This paper reports the accelerated neutron testing on a 90-nm CMOS SRAM that exhibits an increased multiple-bit upset FIT rate from neutrons at large angles of incidence. The modeling of these data is used to predict the reliability of ground-based systems.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TDMR.2008.2002356</doi><tpages>6</tpages></addata></record> |
fulltext | fulltext |
identifier | ISSN: 1530-4388 |
ispartof | IEEE transactions on device and materials reliability, 2008-09, Vol.8 (3), p.565-570 |
issn | 1530-4388 1558-2574 |
language | eng |
recordid | cdi_proquest_miscellaneous_36331142 |
source | IEEE Xplore (Online service) |
subjects | Accelerated tests Angle of incidence Circuit testing Circuits CMOS CMOS technology Devices Error correction Incidence Life estimation Mathematical models Multiple-bit upset (MBU) NASA neutron Neutrons Predictive models Protons Random access memory Semiconductor device modeling soft error Soft errors |
title | Increased Rate of Multiple-Bit Upset From Neutrons at Large Angles of Incidence |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-22T08%3A19%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Increased%20Rate%20of%20Multiple-Bit%20Upset%20From%20Neutrons%20at%20Large%20Angles%20of%20Incidence&rft.jtitle=IEEE%20transactions%20on%20device%20and%20materials%20reliability&rft.au=Tipton,%20A.D.&rft.date=2008-09-01&rft.volume=8&rft.issue=3&rft.spage=565&rft.epage=570&rft.pages=565-570&rft.issn=1530-4388&rft.eissn=1558-2574&rft.coden=ITDMA2&rft_id=info:doi/10.1109/TDMR.2008.2002356&rft_dat=%3Cproquest_cross%3E36331142%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c421t-a4cefdb7d72be1d8ee603096dada83afb4197bb15408d427ce611c832c90e9573%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=912280059&rft_id=info:pmid/&rft_ieee_id=4655571&rfr_iscdi=true |