Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors

High frequency processor designs operating at more than 500 MHz and of significant architectural complexity require custom physical design constraints from the inception of the design. New technology introductions such as copper interconnect wiring improve performance but also add complexity in grou...

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Published in:IBM journal of research and development 1999-09, Vol.43 (5.6), p.681-706
Main Authors: Averill, R M, Barkely, K G, Bowen, M A, Camporese, P J
Format: Article
Language:English
Subjects:
Computer architecture
Microprocessors
R&D
Research & development
Systems integration
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container_end_page 706
container_issue 5.6
container_start_page 681
container_title IBM journal of research and development
container_volume 43
creator Averill, R M
Barkely, K G
Bowen, M A
Camporese, P J
description High frequency processor designs operating at more than 500 MHz and of significant architectural complexity require custom physical design constraints from the inception of the design. New technology introductions such as copper interconnect wiring improve performance but also add complexity in ground rules and wiring.
doi_str_mv 10.1147/rd.435.0681
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identifier ISSN: 0018-8646
ispartof IBM journal of research and development, 1999-09, Vol.43 (5.6), p.681-706
issn 0018-8646
0018-8646
2151-8556
language eng
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source IEEE Xplore All Journals; ABI/INFORM Global
subjects Computer architecture
Microprocessors
R&D
Research & development
Systems integration
title Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors
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