Butterfly interconnection network: design of multiplier, flip-flop, and shift register

A 2 × 2 bit multiplier is designed by the use of a butterfly interconnection network. The butterfly topology is also used to design a sequential flip-flop and a multibit parallel-in parallel-out shift register.

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Bibliographic Details
Published in:Applied optics (2004) 1994-03, Vol.33 (8), p.1457-1462
Main Authors: Iftekharuddin, K M, Karim, M A
Format: Article
Language:English
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Description
Summary:A 2 × 2 bit multiplier is designed by the use of a butterfly interconnection network. The butterfly topology is also used to design a sequential flip-flop and a multibit parallel-in parallel-out shift register.
ISSN:1559-128X
DOI:10.1364/AO.33.001457