Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)

• Published in: Microprocessors and microsystems 2010-03, Vol.34 (2), p.102-116
• Main Authors: Kyung, Hyun-min, Park, Gi-ho, Wook Kwak, Jong, Kim, Tae-jin, Park, Sung-Bae
• Format: Article
• Language: English
• Subjects: AMBA AXI; Buses (vehicles); Design engineering; Devices; Dynamical systems; Dynamics; Monitors; Performance analysis; Performance monitor; Semiconductors; SOC; Synchronism; System on chip
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2010.03.001

With the rapid development of semiconductor technology, more complicated systems have been integrated into single chips. However, system performance is not increased in proportion to the gate-count of the system. This is mainly because the optimized design of the system becomes more difficult as the systems become more complicated. Therefore, it is essential to understand the internal behavior of the system and utilize the system resources effectively in the System on Chip (SOC) design. In this paper, we design a Performance Analysis Unit (PAU) for monitoring the AMBA Advanced eXtensible Interface (AXI) bus as a mechanism to investigate the internal and dynamic behavior of an SOC, especially for internal bus activities. A case study with the PAU for an H.264 decoder application is also presented to show how the PAU is utilized in SOC platform. The PAU has the capability to measure major system performance metrics, such as bus latency, amount of bus traffic, contention between master/slave devices, and bus utilization for specific durations. This paper also presents a distributor and synchronization method to connect multiple PAUs to monitor multiple internal buses of large SOC.