Characterization of Parasitic Bipolar Transistors in 45 nm Silicon-on-Insulator Technology

This paper describes the importance of bipolar current gain and diode ideality factor to predictions of single-event circuit responses. It then reports on measurements of parasitic bipolar transistors in 45 nm Silicon-on-Insulator (SOI) technology, and adjustments to the simulation model to match th...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2010-12, Vol.57 (6), p.3234-3238
Main Authors: Wissel, L, Oldiges, P, Dechao Guo
Format: Article
Language:English
Subjects:
Adjustment
Bipolar transistors
Computer simulation
Diodes
Electric circuits
Electrical resistance measurement
Gain
Mathematical models
Parasitic bipolar
Semiconductor devices
Silicon on insulator technology
silicon-on-insulator (SOI) technology
Simulation
Single event upset
single-event effect
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Description
Summary:This paper describes the importance of bipolar current gain and diode ideality factor to predictions of single-event circuit responses. It then reports on measurements of parasitic bipolar transistors in 45 nm Silicon-on-Insulator (SOI) technology, and adjustments to the simulation model to match the measurements.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2010.2076833