A Methodology for Alleviating the Performance Degradation of TMR Solutions

The shrinking of process technologies in conjunction to the manufacturing and transient faults may be abundant in high density reconfigurable architectures. Design of reliable applications on such unreliable architectures requires techniques able to provide a balance between the desired fault maskin...

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Bibliographic Details
Published in:IEEE embedded systems letters 2010-12, Vol.2 (4), p.111-114
Main Authors: Siozios, K, Soudris, D
Format: Article
Language:English
Subjects:
Architecture
Design engineering
Fault tolerance
Fault tolerant systems
Faults
Field programmable gate arrays
Gate arrays
High density
Masking
Methodology
Mitigation costs
Performance degradation
reconfigurable architecture
Reconfigurable architectures
Redundancy
Reliability
triple modular redundancy (TMR)
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Summary:The shrinking of process technologies in conjunction to the manufacturing and transient faults may be abundant in high density reconfigurable architectures. Design of reliable applications on such unreliable architectures requires techniques able to provide a balance between the desired fault masking and the associated performance and power degradation. Starting from a well established solution for reliability improvement in field-programmable gate arrays (FPGAs) domain, we discuss a software-supported methodology that removes redundancy as much as possible from the design without affecting it's efficiency in terms of fault masking. Based on experimental results, our proposed methodology achieves comparable fault masking with commercial solutions, but in reasonable lower mitigation cost.
ISSN:1943-0663
1943-0671
DOI:10.1109/LES.2010.2083632