Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design

Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit te...

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Bibliographic Details
Published in:IEEE design & test of computers 2011-01, Vol.28 (1), p.22-31
Main Authors: Hamzaoglu, Fatih, Yih Wang, Kolar, Pramod, Liqiong Wei, Yong-Gee Ng, Bhattacharya, Uddalak, Zhang, Kevin
Format: Article
Language:English
Subjects:
Circuit design
Circuit synthesis
Circuits
design and test
Embedded systems
high-performance applications
low power
Low voltage
Memory
minimum operating voltage
Nanocomposites
Nanomaterials
Nanostructure
Optimization
SRAM
SRAM chips
Static random access memory
VCCmin
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Description
Summary:Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes.
ISSN:0740-7475
2168-2356
1558-1918
2168-2364
DOI:10.1109/MDT.2011.5