High-Performance Double-Channel Poly-Silicon Thin-Film Transistor With Raised Drain and Reduced Drain Electric Field Structures

• Published in: IEEE transactions on electron devices 2009-03, Vol.56 (3), p.441-447
• Main Authors: CHIEN, Feng-Tso, LIAO, Chien-Nan, FANG, Chin-Mu, TSAI, Yao-Tsung
• Format: Article
• Language: English
• Subjects: Applied sciences; Channels; Current measurement; Devices; Double-channel poly-Si thin-film transistor (DCTFT); Drains; Electric fields; Electronics; Exact sciences and technology; Leakage current; Logic gates; Periodic structures; Plates (structural members); raised source/drain (RSD); Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Stress; Thin film transistors; Thin films; Threshold voltage; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2008.2011844

In this paper, a high-performance single-gate double-channel polycrystalline-silicon thin-film transistor (DCTFT) is proposed and experimentally demonstrated for the first time. Two thin channels, accompanied with a raised source/drain (S/D) area, an offset structure, a drain field plate, and a field-induced drain region, are used in this device, allowing a lower S/D resistance and a better device performance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability, such as threshold voltage shift and drain on-current degradation under a high gate bias, is also improved by the design of two channels and the reduced drain electric field structures. The lower drain electric field of the DCTFT is also beneficial to scaling down the device for a better performance.