An H.264 video decoder based on a latest generation DSP

Latest generation DSPs are becoming more efficient, being able to improve their forerunners while reducing their internal memory size to lower the cost. In this paper, an H.264 video decoder based on a latest generation DSP is described. Both the EDMA and the memory architecture of the processor hav...

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Bibliographic Details
Published in:IEEE transactions on consumer electronics 2009-02, Vol.55 (1), p.205-212
Main Authors: Pescador, F., Maturana, G., Garrido, M.J., Juarez, E., Sanz, C.
Format: Article
Language:English
Subjects:
Costs
Decoders
Decoding
Digital signal processing
Digital TV
Electronics
H264
IEC standards
ISO standards
Latest Generation DSP
Memory architecture
Microprocessors
Optical discs
Running
Software Optimization
Streaming media
Streams
Television
Testing
Video coding
Video Decoder
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Description
Summary:Latest generation DSPs are becoming more efficient, being able to improve their forerunners while reducing their internal memory size to lower the cost. In this paper, an H.264 video decoder based on a latest generation DSP is described. Both the EDMA and the memory architecture of the processor have been fully exploited to increase the execution speed. Profiling tests have been carried out by using digital TV streams and DVD transcoded sequences. The speed of the new DSP running the decoder is 16% better than that of a forerunner with 20% more internal memory running the same decoder.
ISSN:0098-3063
1558-4127
DOI:10.1109/TCE.2009.4814436