Embedded Vision Modules for Tracking and Counting People

This paper shows the algorithm implementation for a field-programmable gate array (FPGA)-based design for people counting using a low-level head-detection method. The hardware (HW) implementation on an FPGA allows the capture and online processing in real time on the same chip. Different annular pat...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on instrumentation and measurement 2009-09, Vol.58 (9), p.3004-3011
Main Authors: Vicente, A.G., Munoz, I.B., Molina, P.J., Galilea, J.L.L.
Format: Article
Language:English
Subjects:
Algorithm design and analysis
Algorithms
Cameras
Circuits
Costs
Counting
Counting circuit
Extraction
Face detection
Field programmable gate arrays
field-programmable gate arrays (FPGAs)
filtering
Fires
Hardware
hardware (HW) design languages
Head
Hough transforms
Image edge detection
image processing
Instrumentation
pipeline processing
Preprocessing
Real time
video camera
Vision
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper shows the algorithm implementation for a field-programmable gate array (FPGA)-based design for people counting using a low-level head-detection method. The hardware (HW) implementation on an FPGA allows the capture and online processing in real time on the same chip. Different annular patterns are used to process in parallel the image and detect heads of different sizes. Preprocessing and edge extraction are also made using reconfigurable HW. The developed system exploits HW processing, as the vision algorithm has been modified and tuned for HW implementation. It uses minimal area resources of a Spartan3 (1.5 Mgates), and its real-time performance is comparable with more sophisticated algorithms while utilizing very low cost circuits.
ISSN:0018-9456
1557-9662
DOI:10.1109/TIM.2009.2016809