3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot

• Published in: Proceedings of the IEEE 2009-01, Vol.97 (1), p.96-107
• Main Authors: Marchal, Paul, Bougard, Bruno, Katti, Guruprasad, Stucchi, Michele, Dehaene, Wim, Papanikolaou, Antonis, Verkest, Diederik, Swinnen, Bart, Beyne, Eric
• Format: Article
• Language: English
• Subjects: Costs; Crystallization; Design automation; design centering; Design engineering; Electronics industry; Foundries; integrated circuit design; Integrated circuit interconnections; Integrated circuit technology; Law; Logic testing; Markets; Methodology; Moore's Law; Semiconductors; Silicon carbide; Space technology; Strategy; Systems design; technology assessment; Three dimensional
• ISSN: 0018-9219; 1558-2256
• DOI: 10.1109/JPROC.2008.2007471

It is widely acknowledged that three-dimensional (3-D) technologies offer numerous opportunities for system design. In recent years, significant progress has been made on these 3-D technologies, and they have become probably the best hope for carrying the semiconductor industry beyond the path of Moore's law. However, a clear roadmap is missing to successfully introduce this 3-D technology onto the market. Today, a plurality of 3-D technology options exists, which requires different design and test strategies. To crystallize the many technology options in a few mainstream technologies, it is mandatory to coexplore both technology and design options. The contribution of this paper is to introduce a novel path finding methodology to untangle the many intertwined design/technology options. This holistic approach will be applied on a representative 3-D case study. Initial results demonstrate the benefits of the proposed path-finding methodology to steer the technology development and fine-tune design strategies.