C-CREST Technique for Combinational Logic SET Testing

SEUs due to combinational logic in 90 nm CMOS is analyzed at various speeds using a new design approach called the combinational circuit for radiation effects self-test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design w...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2008-12, Vol.55 (6), p.3347-3351
Main Authors: Ahlbin, J.R., Black, J.D., Massengill, L.W., Amusan, O.A., Balasubramanian, A., Casey, M.C., Black, D.A., McCurdy, M.W., Reed, R.A., Bhuva, B.L.
Format: Article
Language:English
Subjects:
Built-in self-test
Circuit design
Circuit testing
CMOS
CMOS logic circuits
CMOS process
Combinational circuits
Combinational logic
Cross sections
Delay
DICE latch
Latches
Logic
Logic design
Logic testing
Permissible error
Propagation delay
Radiation effects
single event
Single event transient
single event upset
window of vulnerability
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Summary:SEUs due to combinational logic in 90 nm CMOS is analyzed at various speeds using a new design approach called the combinational circuit for radiation effects self-test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design was fabricated in IBM's 9SF CMOS process and underwent broadbeam testing that distinguished combinational logic errors from latch errors. Results confirm that the design is effective in testing combinational logic for SE vulnerabilities with minimum speed penalty.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2008.2005900