Multi-Lookup Table FPGA Implementation of an Adaptive Digital Predistorter for Linearizing RF Power Amplifiers With Memory Effects

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA be...

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Bibliographic Details
Published in:IEEE transactions on microwave theory and techniques 2008-02, Vol.56 (2), p.372-384
Main Authors: Gilabert, P.L., Cesari, A., Montoro, G., Bertran, E., Dilhac, J.-M.
Format: Article
Language:English
Subjects:
Algorithms
Amplifiers
Applied sciences
Bandwidth
Broadband amplifiers
Circuit properties
Devices
Digital
Digital circuits
Digital predistortion (DPD)
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
field programmable gate array (FPGA)
Field programmable gate arrays
Hardware
Linearity
Lookup tables
Multiaccess communication
nonlinear auto-regressive moving average (NARMA) models
power amplifier (PA) linearization
Power amplifiers
Predistortion
Radio frequencies
Radio frequency
Radiofrequency amplifiers
Recursive
Studies
Table lookup
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Summary:This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.
ISSN:0018-9480
1557-9670
DOI:10.1109/TMTT.2007.913369