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Effects of Film Stress Modulation Using TiN Metal Gate on Stress Engineering and Its Impact on Device Characteristics in Metal Gate/High-[Formula Omitted] Dielectric SOI FinFETs

In this letter, the effects of TiN-induced strain engineering on device characteristics for a metal gate/high-k silicon-on-insulator fin-shaped field-effect transistors were studied. From a convergent-beam electron-diffraction analysis and simulation study, a 3-nm TiN electrode was found to lead to...

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Published in:IEEE electron device letters 2008-05, Vol.29 (5), p.487-490
Main Authors: Kang, Chang Yong, Yang, Ji-Woon, Oh, Jungwoo, Choi, Rino, Suh, Young Jun, Floresca, H.C, Kim, Jiyoung, Kim, Moon, Lee, Byoung Hun, Tseng, Hsing-Huang, Jammy, R
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container_end_page 490
container_issue 5
container_start_page 487
container_title IEEE electron device letters
container_volume 29
creator Kang, Chang Yong
Yang, Ji-Woon
Oh, Jungwoo
Choi, Rino
Suh, Young Jun
Floresca, H.C
Kim, Jiyoung
Kim, Moon
Lee, Byoung Hun
Tseng, Hsing-Huang
Jammy, R
description In this letter, the effects of TiN-induced strain engineering on device characteristics for a metal gate/high-k silicon-on-insulator fin-shaped field-effect transistors were studied. From a convergent-beam electron-diffraction analysis and simulation study, a 3-nm TiN electrode was found to lead to significantly higher tensile stress on the Si substrate than a 20-nm TiN electrode. This high stress-induced fast bulk carrier generation results in the transient current-time characteristics. Therefore, 3- and 20-nm TiN electrodes are the excellent choice for nMOSFETs and pMOSFETs, respectively, which is from the standpoint of strain engineering, threshold voltage (V@@dth@), and performance. Due to the metal-induced strain, I@@ddsat@ improvements of 15% and 12% for nMOSFETs and pMOSFETs, respectively, were achieved.
doi_str_mv 10.1109/LED.2008.919782
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subjects Current carriers
Devices
Electrodes
Gates
Modulation
Strain
Stresses
Titanium nitride
title Effects of Film Stress Modulation Using TiN Metal Gate on Stress Engineering and Its Impact on Device Characteristics in Metal Gate/High-[Formula Omitted] Dielectric SOI FinFETs
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