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Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs

A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2008-12, Vol.16 (12), p.1717-1721
Main Authors: Popovich, M., Friedman, E.G., Secareanu, R.M., Hartin, O.L.
Format: Article
Language:English
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Summary:A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2008.2001735