Effective Radii of On-Chip Decoupling Capacitors

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard cell circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impeda...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2008-07, Vol.16 (7), p.894-907
Main Authors: Popovich, M., Sotman, M., Kolodny, A., Friedman, E.G.
Format: Article
Language:English
Subjects:
Applied sciences
Capacitance
Capacitors
Charge
Circuit noise
Criteria
Decoupling
Decoupling capacitors
Design methodology
Dielectric, amorphous and glass solid devices
Electrical engineering. Electrical power engineering
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Impedance
Joining processes
Noise reduction
Power distribution
power distribution systems
Power electronics, power supplies
Power supplies
power supply noise
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
signal integrity
Very large scale integration
Voltage
White spaces
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Summary:Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard cell circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A design methodology for placing on-chip decoupling capacitors is presented in this paper. A maximum effective radius is shown to exist for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is ineffective. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop seen at the current load is caused either by the first droop (determined by the rise time) or by the second droop (determined by the transition time). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. In order to provide the required charge drawn by the load, the decoupling capacitor has to be charged before the next switching cycle. For an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2008.2000454