A 40-44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2007-12, Vol.42 (12), p.2726
Main Authors: Nedovic, N, Tzartzanis, N, Tamura, H, Rotella, F.M, Wiklund, M, Mizutani, Y, Okaniwa, Y, Kuroda, T, Ogawa, J, Walker, W.W
Format: Article
Language:English
Subjects:
Circuits
Clocks
CMOS
Digital
Dissipation
Jitter
Oversampling
Tolerances
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Summary:A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2007.908714