Low-Power High-Performance Asymmetrical Double-Gate Circuits Using Back-Gate-Controlled Wide-Tunable-Range Diode Voltage

This paper presents a new power-reduction scheme using a back-gate-controlled asymmetrical double-gate device with robust data-retention capability for high-performance logic/SRAM power gating or variable/dynamic supply applications. The scheme reduces the transistor count, area, and capacitance in...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2007-09, Vol.54 (9), p.2263-2268
Main Authors: Keunwoo Kim, Ching-Te Chuang, Kuang, J.B., Ngo, H.C., Nowka, K.J.
Format: Article
Language:English
Subjects:
Asymmetrical double-gate (DG) device
Asymmetry
back gate
Circuits
Clamps
Devices
Dynamics
Electric potential
Gating and risering
Latches
Leakage current
Logic gates
mix-mode simulator
power gating
Random access memory
Silicon
Static random access memory
Switches
Voltage
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Summary:This paper presents a new power-reduction scheme using a back-gate-controlled asymmetrical double-gate device with robust data-retention capability for high-performance logic/SRAM power gating or variable/dynamic supply applications. The scheme reduces the transistor count, area, and capacitance in the header/footer device and provides a wide range of virtual ground (GND) or supply voltage. Physical analysis and numerical mix-mode device/circuit-simulation results confirm that the proposed scheme can be applied to low-power high-performance circuit applications in 65-nm technology node and beyond. Variable/dynamic supply or GND voltage using the proposed scheme improves read and write margins in scaled SRAM without degrading read and write performance.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2007.902693