Exploration and Customization of FPGA-Based Soft Processors

As embedded systems designers increasingly use field-programmable gate arrays (FPGAs) while pursuing single-chip designs, they are motivated to have their designs also include soft processors, processors built using FPGA programmable logic. In this paper, we provide: 1) an exploration of the microar...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2007-02, Vol.26 (2), p.266-277
Main Authors: Yiannacouras, P., Steffan, J.G., Rose, J.
Format: Article
Language:English
Subjects:
Application software
Computer aided design
Customization
Design
Design engineering
design space exploration
Embedded system
Exploration
Field programmable gate arrays
field programmable gate-array (FPGA)-based soft-core processors
Gate arrays
Hardware
Integrated circuits
Logic design
Logic devices
Logic programming
Microarchitecture
processor generator
Processors
Programmable logic arrays
Programmable logic controllers
Space exploration
Tuning
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Summary:As embedded systems designers increasingly use field-programmable gate arrays (FPGAs) while pursuing single-chip designs, they are motivated to have their designs also include soft processors, processors built using FPGA programmable logic. In this paper, we provide: 1) an exploration of the microarchitectural tradeoffs for soft processors and 2) a set of customization techniques that capitalizes on these tradeoffs to improve the efficiency of soft processors for specific applications. Using our infrastructure for automatically generating soft-processor implementations (which span a large area/speed design space while remaining competitive with Altera's Nios II variations), we quantify tradeoffs within soft-processor microarchitecture and explore the impact of tuning the microarchitecture to the application. In addition, we apply a technique of subsetting the instruction set to use only the portion utilized by the application. Through these two techniques, we can improve the performance-per-area of a soft processor for a specific application by an average of 25%
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2006.887921