Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

• Published in: IEEE transactions on electron devices 2006-05, Vol.53 (5), p.1169-1179
• Main Authors: Tada, M., Tamura, T., Ito, F., Ohtake, H., Narihiro, M., Tagami, M., Ueki, M., Hijioka, K., Abe, M., Inoue, N., Takeuchi, T., Saito, S., Onodera, T., Furutake, N., Arai, K., Sekine, M., Suzuki, M., Hayashi, Y.
• Format: Article
• Language: English
• Subjects: 65-nm node; Applied sciences; Breakdown; CHEMICAL VAPOR DEPOSITION; CONNECTORS (ELECTRICAL); Copper; damascene; Design. Technologies. Operation analysis. Testing; DIELECTRIC BREAKDOWN; Dielectric materials; Dielectrics; Electric breakdown; ELECTROMIGRATION; Electronics; Exact sciences and technology; Integrated circuit interconnections; Integrated circuit reliability; INTEGRATED CIRCUITS; interconnects; INTERLAYERS; LINERS; Microelectronic fabrication (materials and surfaces technology); Plasma CVD; POROSITY; porous dielectric (porous low; Porous materials; reliability; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon compounds; SILICON DIOXIDE; Ultra Large Scale Integration
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2006.872095

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.