High-Efficiency LDMOS Power-Amplifier Design at 1 GHz Using an Optimized Transistor Model

A 10-W LDMOS harmonically tuned power amplifier at 1 GHz with state-of-the-art power-added efficiency of 80% is presented. The fundamental and second-harmonic load impedances are optimized for maximum efficiency while other harmonics are blocked by a low-pass load network. A simplified model of the...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on microwave theory and techniques 2009-07, Vol.57 (7), p.1647-1654
Main Authors: Nemati, H.M., Fager, C., Thorsell, M., Zirath, H.
Format: Article
Language:English
Subjects:
Accuracy
Amplifiers
Applied sciences
Blocking
Capacitance
Circuit properties
Computer simulation
Design optimization
Electric, optical and optoelectronic circuits
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Frequency
Gallium nitride
Harmonically tuned
High power amplifiers
Impedance
LDMOS
Microwave technology
Microwaves
Power amplifier
power amplifier (PA)
Power amplifiers
Semiconductor devices
State of the art
Switched mode
Switches
Transistors
Voltage
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A 10-W LDMOS harmonically tuned power amplifier at 1 GHz with state-of-the-art power-added efficiency of 80% is presented. The fundamental and second-harmonic load impedances are optimized for maximum efficiency while other harmonics are blocked by a low-pass load network. A simplified model of the transistor specialized for harmonically tuned and switched mode operations is proposed and used for the design. Good agreement between simulations and measurements is observed, indicating high accuracy of the model and design approach for these particular applications.
ISSN:0018-9480
1557-9670
1557-9670
DOI:10.1109/TMTT.2009.2022590