BIST for network on chip communication infrastructure based on combination of extended I II 1149.1 and I II 1500 standards

In this paper we propose a BIST based method to test network on chip (NOC) communication infrastructure. The proposed method utilizes an I II 1149.1 architecture based on BIST to at-speed test of crosstalk faults for inter-switch links as well as an I II 1500-compliant wrapper to test switches thems...

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Bibliographic Details
Published in:Microelectronics 2011-05, Vol.42 (5), p.667-680
Main Authors: Nourmandi-Pour, Reza, Mousavian, Nafiseh, Khadem-Zadeh, Ahmad
Format: Article
Language:English
Subjects:
Architecture
Chips
Infrastructure
Links
Networks
Switches
Switching theory
Online Access:Get full text
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Summary:In this paper we propose a BIST based method to test network on chip (NOC) communication infrastructure. The proposed method utilizes an I II 1149.1 architecture based on BIST to at-speed test of crosstalk faults for inter-switch links as well as an I II 1500-compliant wrapper to test switches themselves in NOC communication infrastructure. The former architecture includes enhanced cells intended for MAF model test patterns generation and analysis test responses, and the later architecture includes: (a) a March decoder which decodes and executes March commands, which are scanned in serially from input system, on First-In-First-Out (FIFO) buffers in the switch; and (b) a scan chain which is defined to test routing logic block of the switch. To at-speed test inter-switch links one new instruction is used to control cells and TPG controller. Two new instructions, as well as, are applied to activate March decoder and to control scan activities in switch test session. These instructions are defined to fully comply with conventional I II 1149.1 and I II 1500 standards.
ISSN:0026-2692
DOI:10.1016/j.mejo.2011.03.002