Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking

This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in...

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Bibliographic Details
Published in:Microelectronic engineering 2011-05, Vol.88 (5), p.729-733
Main Authors: Eid, E., Lacrevaz, T., Bermond, C., Capraro, S., Roullard, J., Fléchet, B., Cadix, L., Farcy, A., Ancey, P., Calmon, F., Valorge, O., Leduc, P.
Format: Article
Language:English
Subjects:
3D integration
Applied sciences
Capacitive, conductive and inductive coupling
Computer simulation
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Integrated circuits
Joining
Mathematical models
Microwave
Radio frequencies
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon substrate
Silicon substrates
Stacking
Testing, measurement, noise and reliability
Three dimensional
Through Silicon Vias (TSV)
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Summary:This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise.
ISSN:0167-9317
1873-5568
DOI:10.1016/j.mee.2010.07.013