Efficient built-in redundancy analysis for embedded memories with 2-D redundancy

A novel redundant mechanism is proposed for embedded memories in this paper. Redundant rows and columns are added into the memory array as in the conventional approaches. However, the redundant rows and columns are divided into row blocks and column blocks, respectively. The reconfiguration is perfo...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2006-01, Vol.14 (1), p.34-42
Main Authors: Shyue-Kung Lu, Yu-Chen Tsai, Hsu, C.-H., Kuo-Hua Wang, Cheng-Wen Wu
Format: Article
Language:English
Subjects:
Algorithms
Allocations
Applied sciences
Arrays
Complexity
Design. Technologies. Operation analysis. Testing
Electronics
Electronics industry
Embedded memory
Exact sciences and technology
Fabrication
Fault tolerance
Hardware
Integrated circuits
Integrated circuits by function (including memories and processors)
Logic
Magnetic and optical mass memories
Random access memory
Read-write memory
Redundancy
redundancy analysis
Redundant
reliability
repair rate
Semiconductor device manufacture
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
Storage and reproduction of information
Very large scale integration
yield
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Summary:A novel redundant mechanism is proposed for embedded memories in this paper. Redundant rows and columns are added into the memory array as in the conventional approaches. However, the redundant rows and columns are divided into row blocks and column blocks, respectively. The reconfiguration is performed at the row (column) block level instead of the conventional row (column) level. Based on the proposed redundant mechanism, we first show that the complexity of the redundancy allocation problem is NP-complete. Thereafter, an extended local repair-most (ELRM) algorithm suitable for built-in implementation is proposed. The complexity of the ELRM algorithm is O(N), where N denotes the number of memory cells. According to the simulation results, the hardware overhead for implementing this algorithm is below 0.17% for a 1024/spl times/2048-b SRAM. Due to the efficient usage of the redundant elements, the manufacturing yield, repair rate, and reliability can be improved significantly.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2005.863189