Physical analysis of breakdown in high-[kappa]/metal gate stacks using TEM/EELS and STM for reliability enhancement (invited)

In this invited paper, we demonstrate how physical analysis techniques that are commonly used in integrated circuits failure analysis can be applied to detect the failure defects associated with ultrathin gate dielectric wear-out and breakdown in high-[kappa] materials and investigate the associated...

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Bibliographic Details
Published in:Microelectronic engineering 2011-07, Vol.88 (7), p.1365-1372
Main Authors: Pey, Kin Leong, Raghavan, Nagarajan, Wu, Xing, Liu, Wenhu, Li, Xiang, Bosman, Michel, Shubhakar, Kalya, Lwin, Zin Zar, Chen, Yining, Qin, Hailang, Kauerauf, Thomas
Format: Article
Language:English
Subjects:
Breakdown
Defects
Electrodes
Failure
Failure mechanisms
Gates
Hafnium
Nanostructure
Online Access:Get full text
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Summary:In this invited paper, we demonstrate how physical analysis techniques that are commonly used in integrated circuits failure analysis can be applied to detect the failure defects associated with ultrathin gate dielectric wear-out and breakdown in high-[kappa] materials and investigate the associated failure mechanism(s) based on the defect chemistry. The key contributions of this work are perhaps focused on two areas: (1) how to correlate the failure mechanisms in high-[kappa]/metal gate technology during wear-out and breakdown to device processing and materials and (2) how the understanding of these new failure mechanisms can be used in proposing "design for reliability" (DFR) initiatives for complex and expensive future CMOS nanoelectronic technology nodes of 22 nm and 15 nm. Hf-based high-[kappa] materials in conjunction with various gate electrode technologies will be used as main examples while other potential high-[kappa] gate materials such as cerium oxide (CeO sub(2) will also be demonstrated to further illustrate the concept of DFR.)
ISSN:0167-9317
DOI:10.1016/j.mee.2011.03.012