Accurate analysis of parasitic current overshoot during forming operation in RRAMs

• Published in: Microelectronic engineering 2011-07, Vol.88 (7), p.1129-1132
• Main Authors: Tirano, S., Perniola, L., Buckley, J., Cluzel, J., Jousseaume, V., Muller, Ch, Deleruyelle, D., De Salvo, B., Reimbold, G.
• Format: Article
• Language: English
• Subjects: Applied sciences; Architecture; Circuit properties; Current overshoot; Data storage; Devices; Electric, optical and optoelectronic circuits; Electroforming; Electronic circuits; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Exact sciences and technology; Forming; Hafnium oxide; Integrated circuits; Integrated circuits by function (including memories and processors); Magnetic and optical mass memories; Memory devices; Memory operations; Parasitic capacitance; Resistive switching memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Storage and reproduction of information; Switching, multiplexing, switched capacity circuits
• ISSN: 0167-9317; 1873-5568
• DOI: 10.1016/j.mee.2011.03.062

In this paper overshoot current during forming operation in RRAM devices with different oxides and thickness was investigated. None of the methods used were able to limit properly this current during operation. [Display omitted] ► We analyzed current overshoot during forming operation in RRAM devices. ► Current overshoot was measured in HfO 2- and NiO-based devices for 10nm- and 20nm-thick oxide. ► This current is provided by parasitic capacitance discharge in 1R device architecture. ► Any of the methods we experimented were able to limit properly the overshoot in the switching transient. In this paper, a peculiar attention is turned towards the understanding of the current overshoot occurring during the forming operation in resistive switching memory devices. This phenomenon is attributed to the discharge of a parasitic capacitance in parallel to the resistive device in simple 1R (one resistor, no transistor/diode selector) architectures. The impact of such an overshoot is analyzed on both NiO and HfO 2-based memory elements by performing measurements with different setups (quasi-static and pulse measurements). We show that the parasitic event is more severe as the forming voltage in the memory device increases. Moreover, it is shown that the post-forming resistance cannot be simply adjusted by a current compliance available on semiconductor parameter analyzers, since this internal limiter is ineffective in the microsecond range for compliance levels lower than the current spike. The current overshoot playing a detrimental role on the electrical performances of resistive devices, it must be carefully monitored when assessing the electrical performances in simple 1R architectures.