An 800-MHz embedded DRAM with a concurrent refresh mode

An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refre...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2005-06, Vol.40 (6), p.1377-1387
Main Authors: Kirihata, T., Parries, P., Hanson, D.R., Hoki Kim, Golz, J., Fredeman, G., Rajeevakumar, R., Griesemer, J., Robson, N., Cestero, A., Khan, B.A., Geng Wang, Wordeman, M., Iyer, S.S.
Format: Article
Language:English
Subjects:
Applied sciences
Arrays
Cache memory
Circuit properties
Clocks
Command multiplier
Commands
concurrent refresh mode
Devices
Dynamic random access memory
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
embedded DRAM
Exact sciences and technology
Frequency
Hardware
high-performance cell
Input-output equipment
Integrated circuits
Integrated circuits by function (including memories and processors)
Logic
Logic devices
Logic testing
Low frequencies
Magnetic and optical mass memories
Random access memory
Redundancy
refresh scheduler
Registers
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
Signal generators
Storage and reproduction of information
Threshold voltage
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Summary:An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2005.848019