A 60 mW per Lane, 4 23-Gb/s 2 1 PRBS Generator

An ultra-low-power, 2 super(7)-1 PRBS generator with four, appropriately delayed, parallel output streams was designed. It was fabricated in a 150-GHz f sub(T) SiGe BiCMOS technology and measured to work up to 23 Gb/s. The four-channel PRBS generator consumes 235 mW from 2.5 V, which results in only...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2006-10, Vol.41 (10), p.2198
Main Authors: Laskin, E, Voinigescu, S.P
Format: Article
Language:English
Subjects:
Circuits
Consumption
Generators
Lanes
Latches
Power consumption
Silicon germanides
Topology
Online Access:Get full text
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Summary:An ultra-low-power, 2 super(7)-1 PRBS generator with four, appropriately delayed, parallel output streams was designed. It was fabricated in a 150-GHz f sub(T) SiGe BiCMOS technology and measured to work up to 23 Gb/s. The four-channel PRBS generator consumes 235 mW from 2.5 V, which results in only 60 mW per output lane. The circuit is based on a 2.5-mW BiCMOS CML latch topology, which, to the best of our knowledge, represents the lowest power for a latch operating above 10 Gb/s. A power consumption and speed comparison of series and parallel PRBS generation techniques is presented. Low-power BiCMOS CML latch topologies are analyzed using the OCTC method
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2006.878112