Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. M...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2006-05, Vol.41 (5), p.1100-1107
Main Authors: KER, Ming-Dou, CHEN, Shih-Lun, TSAI, Chia-Shen
Format: Article
Language:English
Subjects:
Applied sciences
Body effect
Charge measurement
charge pump circuit
Charge pumps
Charge transfer
Circuit design
Circuit properties
Circuit testing
Circuits
CMOS
CMOS process
Current measurement
Design
Design. Technologies. Operation analysis. Testing
Electric potential
Electric, optical and optoelectronic circuits
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
gate-oxide reliability
high-voltage generator
Integrated circuits
low voltage
Power supplies
Power supply
Pumping
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
Switches
Switching circuits
Switching, multiplexing, switched capacity circuits
Voltage
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Summary:A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-/spl mu/m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2006.872704