Floorplanning With Wire Pipelining in Adaptive Communication Channels

The recent shift toward wire pipelining (WP) mandated by technological factors has attracted attention toward latency-controlled floorplanning. However, no systematic study has been published so far that takes into account block and logic-delay limitations. This paper aims at filling the gap by show...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2006-12, Vol.25 (12), p.2996-3004
Main Authors: Casu, M.R., Macchiarulo, L.
Format: Article
Language:English
Subjects:
Blocking
Channels
CMOS logic circuits
CMOS technology
Communication channels
Decoding
Delay
Filling
Floorplanning
Frequency
Gain
MPEG encoders
Optimization
Pipeline processing
Pipelining (computers)
Scalability
systems-on-chip
Wire
wire pipelining (WP)
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Summary:The recent shift toward wire pipelining (WP) mandated by technological factors has attracted attention toward latency-controlled floorplanning. However, no systematic study has been published so far that takes into account block and logic-delay limitations. This paper aims at filling the gap by showing that block delay can limit and possibly prevent any real gain WP might promise. In this paper, the authors also show how a modified adaptive WP scheme, on the other hand, allows relevant gains. They built a SoC floorplanner based on the use of adaptive and nonadaptive WP, which optimizes the data rate, taking block delay into account. The results of new and old WP techniques applied on benchmarks and on an MPEG decoder are compared to the optimal results obtained when no WP is employed
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2006.882590