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High-speed high-precision CMOS analog rank order filter with O(n) complexity
A continuous-time implementation of a voltage-mode analog rank order filter is presented. The proposed circuit features high speed, high precision, and simple circuit implementation. The overall architecture exhibits linear increase of complexity with the number of inputs (O(n)), at the rate of seve...
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Published in: | IEEE journal of solid-state circuits 2005-06, Vol.40 (6), p.1238-1248 |
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container_issue | 6 |
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container_title | IEEE journal of solid-state circuits |
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creator | Carvajal, R.G. Ramirez-Angulo, J. Ducoudray, G.O. Lopez-Martin, A.J. |
description | A continuous-time implementation of a voltage-mode analog rank order filter is presented. The proposed circuit features high speed, high precision, and simple circuit implementation. The overall architecture exhibits linear increase of complexity with the number of inputs (O(n)), at the rate of seven transistors per input. Rank is easily programmable with the tail current for all rank order values from the Max to the Min case, and the programmed function is accurate for a wide range of tail currents. Moreover, unlike previously reported rank order structures the precision of the proposed circuit does not rely on perfect matching of all input transistors. Simulations as well as experimental results are presented that verify the functionality and performance of the proposed circuit. |
doi_str_mv | 10.1109/JSSC.2005.848025 |
format | article |
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The proposed circuit features high speed, high precision, and simple circuit implementation. The overall architecture exhibits linear increase of complexity with the number of inputs (O(n)), at the rate of seven transistors per input. Rank is easily programmable with the tail current for all rank order values from the Max to the Min case, and the programmed function is accurate for a wide range of tail currents. Moreover, unlike previously reported rank order structures the precision of the proposed circuit does not rely on perfect matching of all input transistors. Simulations as well as experimental results are presented that verify the functionality and performance of the proposed circuit.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2005.848025</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Analog array processing ; Applied sciences ; Array signal processing ; Cellular neural networks ; Circuit properties ; Circuits ; CMOS ; Complexity ; Design. Technologies. Operation analysis. Testing ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Filtering ; Filters ; Frequency filters ; High speed ; Image processing ; Impedance matching ; Integrated circuits ; Matching ; order statistic filtering ; ranked order filter ; Semiconductor devices ; Semiconductor electronics. Microelectronics. Optoelectronics. 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The proposed circuit features high speed, high precision, and simple circuit implementation. The overall architecture exhibits linear increase of complexity with the number of inputs (O(n)), at the rate of seven transistors per input. Rank is easily programmable with the tail current for all rank order values from the Max to the Min case, and the programmed function is accurate for a wide range of tail currents. Moreover, unlike previously reported rank order structures the precision of the proposed circuit does not rely on perfect matching of all input transistors. Simulations as well as experimental results are presented that verify the functionality and performance of the proposed circuit.</description><subject>Analog array processing</subject><subject>Applied sciences</subject><subject>Array signal processing</subject><subject>Cellular neural networks</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>CMOS</subject><subject>Complexity</subject><subject>Design. Technologies. Operation analysis. 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The proposed circuit features high speed, high precision, and simple circuit implementation. The overall architecture exhibits linear increase of complexity with the number of inputs (O(n)), at the rate of seven transistors per input. Rank is easily programmable with the tail current for all rank order values from the Max to the Min case, and the programmed function is accurate for a wide range of tail currents. Moreover, unlike previously reported rank order structures the precision of the proposed circuit does not rely on perfect matching of all input transistors. Simulations as well as experimental results are presented that verify the functionality and performance of the proposed circuit.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2005.848025</doi><tpages>11</tpages></addata></record> |
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subjects | Analog array processing Applied sciences Array signal processing Cellular neural networks Circuit properties Circuits CMOS Complexity Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Filtering Filters Frequency filters High speed Image processing Impedance matching Integrated circuits Matching order statistic filtering ranked order filter Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Simulation Statistics Tail Transistors Voltage |
title | High-speed high-precision CMOS analog rank order filter with O(n) complexity |
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