A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation

A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2004-01, Vol.39 (1), p.49-62
Main Authors: Pamarti, S., Jansson, L., Galton, I.
Format: Article
Language:English
Subjects:
Bandwidth
Cancellation
Charge pumps
CMOS
Current measurement
Delta modulation
Digital broadcasting
Frequency modulation
Frequency shift keying
Linearization
Linearization techniques
Modulation
Noise
Noise levels
Phase locked loops
Phase noise
Wideband
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Summary:A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2003.820858