Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design

In this letter, the random dopant fluctuation effect in ultrathin-body (UTB) fully depleted/silicon-on-insulator (FD/SOI) devices is analyzed. We show that due to larger variability and asymmetry in threshold voltage V/sub t/ distribution, it will be difficult to use UTB FD/SOI devices for sub-50-nm...

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Bibliographic Details
Published in:IEEE electron device letters 2006-04, Vol.27 (4), p.284-287
Main Authors: Mukhopadhyay, S., Keunwoo Kim, Xinlin Wang, Frank, D.J., Oldiges, P., Ching-Te Chuang, Roy, K.
Format: Article
Language:English
Subjects:
Applied sciences
Asymmetry
Circuit stability
Design. Technologies. Operation analysis. Testing
Devices
Doping
Electronics
Exact sciences and technology
Fluctuation
Fluctuations
Fully depleted silicon-on-insulator (SOI)
Integrated circuits
Integrated circuits by function (including memories and processors)
leakage
Optimization
Oxides
Random access memory
random dopant fluctuations (RDFs)
Resource description framework
Robustness
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon on insulator technology
Solvents
Spreads
SRAM chips
stability
Static random access memory
static random access memory (SRAM)
Threshold voltage
Very large scale integration
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Summary:In this letter, the random dopant fluctuation effect in ultrathin-body (UTB) fully depleted/silicon-on-insulator (FD/SOI) devices is analyzed. We show that due to larger variability and asymmetry in threshold voltage V/sub t/ distribution, it will be difficult to use UTB FD/SOI devices for sub-50-nm static random access memory (SRAM) design. Using thinner buried oxide (BOX) FD/SOI devices, the asymmetry in the V/sub t/ spread can be reduced. We present a viable concept of FD/SOI SRAM and predict that a thin-BOX device is the optimal FD/SOI structure for SRAM in sub-50-nm technology nodes.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2006.871540