Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform

In this paper, a detailed analysis of very large scale integration (VLSI) architectures for the one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is presented in many aspects, and three related architectures are proposed as well. The 1-D DWT and inverse DWT (IDWT) arch...

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Bibliographic Details
Published in:IEEE transactions on signal processing 2005-04, Vol.53 (4), p.1575-1586
Main Authors: HUANG, Chao-Tsung, TSENG, Po-Chih, CHEN, Liang-Gee
Format: Article
Language:English
Subjects:
Applied sciences
Architecture
B-spline factorization
Bandwidth
Buffers
Chaos
Convolution
Critical path
Discrete Wavelet Transform
Discrete wavelet transforms
Educational institutions
Exact sciences and technology
Hardware
Information, signal and communications theory
Integrated circuits
Inverse
lifting scheme
line-based method
Memory architecture
Miscellaneous
Registers
Signal processing
Telecommunications and information theory
Very large scale integration
VLSI architecture
Wavelet analysis
Wavelet transforms
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Summary:In this paper, a detailed analysis of very large scale integration (VLSI) architectures for the one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is presented in many aspects, and three related architectures are proposed as well. The 1-D DWT and inverse DWT (IDWT) architectures are classified into three categories: convolution-based, lifting-based, and B-spline-based. They are discussed in terms of hardware complexity, critical path, and registers. As for the 2-D DWT, the large amount of the frame memory access and the die area occupied by the embedded internal buffer become the most critical issues. The 2-D DWT architectures are categorized and analyzed by different external memory scan methods. The implementation issues of the internal buffer are also discussed, and some real-life experiments are given to show that the area and power for the internal buffer are highly related to memory technology and working frequency, instead of the required memory size only. Besides the analysis, the B-spline-based IDWT architecture and the overlapped stripe-based scan method are also proposed. Last, we propose a flexible and efficient architecture for a one-level 2-D DWT that exploits many advantages of the presented analysis.
ISSN:1053-587X
1941-0476
DOI:10.1109/TSP.2005.843704