PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2007-12, Vol.15 (12), p.1311-1319
• Main Authors: Zhiyu Liu, Kursun, V.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; CMOS; CMOS logic circuits; CMOS technology; Design. Technologies. Operation analysis. Testing; Digital circuits; Dynamic CMOS; Electric potential; Electric, optical and optoelectronic circuits; electron tunneling; Electronic circuits; Electronics; Energy consumption; Exact sciences and technology; Field programmable gate arrays; gate oxide tunneling; Gates (circuits); hole leakage; Insulation; Integrated circuits; Leakage; Logic circuits; low-leakage sleep mode; multithreshold voltage; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sleep; Subthreshold current; subthreshold leakage current; Switches; Switching, multiplexing, switched capacity circuits; Transistors; Turning; Voltage
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2007.903947

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.