A burst-mode receiver for 1.25-Gb/s ethernet PON with AGC and internally created reset signal

This paper presents a burst-mode receiver for 1.25-Gb/s Ethernet PON system using mixed-mode CMOS 0.18-/spl mu/m technology. With the modified cell-based AGC function and differential feed-forward topology, the receiver achieves sensitivity of -26.4 dBm, overload of -5.4 dBm, and a loud/soft ratio o...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2004-12, Vol.39 (12), p.2379-2388
Main Authors: LE, Quan, LEE, Sang-Gug, OH, Yong-Hun, KANG, Ho-Yong, YOO, Tae-Hwan
Format: Article
Language:English
Subjects:
Applied sciences
Architecture
Burst-mode
Bursting
cell-based AGC
Circuit properties
CMOS logic circuits
CMOS technology
Consumption
Electric, optical and optoelectronic circuits
Electronics
EPON
Ethernet
Ethernet networks
Exact sciences and technology
feed-forward
Feedforward systems
Integrated optics. Optical fibers and wave guides
Logic
Network topology
Networks
Optical and optoelectronic circuits
optical communication
Optical receivers
Passive optical networks
Receivers
reset
Signal design
Systems, networks and services of telecommunications
Telecommunications
Telecommunications and information theory
Timing
Transmission and modulation (techniques and equipments)
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Summary:This paper presents a burst-mode receiver for 1.25-Gb/s Ethernet PON system using mixed-mode CMOS 0.18-/spl mu/m technology. With the modified cell-based AGC function and differential feed-forward topology, the receiver achieves sensitivity of -26.4 dBm, overload of -5.4 dBm, and a loud/soft ratio of 21 dB while keeping the low-voltage positive emitter-coupled logic (LVPECL) differential output level fully compliant with the ethernet passive optical network (EPON) standard. Unlike other burst-mode receivers, the design obtains fast response even without a reset signal from the network layer by creating a reset signal internally based on the incoming signal. This setting allows for simple system design. The overall architecture and several blocks are optimized in accordance with internal reset creation. Minimum guard time and preamble time are 250 and 50 ns, respectively; all timing parameters are better than the current EPON standard. The prototype contains all components on-chip that occupies 0.9/spl times/1.9 mm/sup 2/ and consumes 160 mA current from a 3.3-V supply.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2004.835644