A Hybrid Framework for Fault Detection, Classification, and Location-Part II: Implementation and Test Results

• Published in: IEEE transactions on power delivery 2011-07, Vol.26 (3), p.1999-2008
• Main Authors: JIANG, Joe-Air, CHUANG, Cheng-Long, WANG, Yung-Chung, HUNG, Chih-Hung, WANG, Jiing-Yi, LEE, Chien-Hsing, HSIAO, Ying-Tung
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit faults; Classification; Computer simulation; Electrical engineering. Electrical power engineering; Electrical power engineering; Evolvable hardware; Exact sciences and technology; fault classification; Fault detection; Fault diagnosis; fault location; Field programmable gate arrays; field-programmable gate array (FPGA); Hardware; Mathematical models; Miscellaneous; Neural networks; Power networks and lines; Principal component analysis; Real time systems; Studies; Support vector machines; Testing. Reliability. Quality control; Training; Wavelet transforms
• ISSN: 0885-8977; 1937-4208
• DOI: 10.1109/TPWRD.2011.2141158

This paper is the second part of a series of two papers addressing a hybrid framework for achieving fault detection, classification, and location, simultaneously. The proposed framework is formed by a variety of analysis techniques, including symmetrical component analysis, wavelet transforms, principal component analysis, support vector machines, and adaptive structure neural networks. In our previous paper, the mathematical foundation of this framework with numerical results obtained by computer-based simulations has been presented. This paper is devoted to discuss the field-programmable gate-array implementation and experimental results acquired by using real-world scenarios. The hardware implementation of the runtime training technique in the proposed framework is an evolvable hardware tested by the power signals used in a power company transmission network for performance evaluation. The runtime training technique allows the FPGA to have learning and re-training capabilities. The main purpose of this paper is to show the applicability of the proposed framework on a hardware platform and test the framework's robustness and evolvability against noises from the system and measurements.