A transition-encoded dynamic bus technique for high-performance interconnects

This paper describes a transition-encoded dynamic bus technique that enables on-chip interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reductio...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2003-05, Vol.38 (5), p.709-714
Main Authors: Anders, M., Rai, N., Krishnamurthy, R.K., Borkar, S.
Format: Article
Language:English
Subjects:
Buses (vehicles)
Capacitance
Circuits
Coupling circuits
Delay
Driver circuits
Dynamics
Encoding
Integrated circuit interconnections
Microprocessors
Reduction
Robustness
Switches
Switching
Timing
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Summary:This paper describes a transition-encoded dynamic bus technique that enables on-chip interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reduction even for short-length buses, while obtaining energy savings at aggressive delay targets. On a 180-nm 32-bit microprocessor, 79% of all global buses exhibit 10%-35% performance improvement using this technique.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2003.810061