A high-throughput low-cost AES processor

We propose an efficient hardware implementation of the advanced encryption standard algorithm, with key expansion capability. Compared to the widely used table lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64 percent. Our pipelined design...

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Bibliographic Details
Published in:IEEE communications magazine 2003-12, Vol.41 (12), p.86-91
Main Authors: Su, Chih-Pin, Lin, Tsung-Fu, Huang, Chih-Tsiun, Wu, Cheng-Wen
Format: Magazinearticle
Language:English
Subjects:
Circuits
Clocks
CMOS
Computational complexity
Costs
Cryptography
Galois fields
Hardware
Inverters
Keys
Polynomials
Table lookup
Tables (data)
Testability
Transformations
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Summary:We propose an efficient hardware implementation of the advanced encryption standard algorithm, with key expansion capability. Compared to the widely used table lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64 percent. Our pipelined design has a very high throughput rate. Using typical 0.35 μm CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate in the non-feedback cipher mode is 2.38 Gb/s for 128-bit keys, 2.008 Gb/s for 192-bit keys, and 1.74 Gb/s for 256-bit keys, respectively. Testability of the design is also considered. The hardware cost of the AES design is approximately 58 K gates using a standard synthesis flow.
ISSN:0163-6804
1558-1896
DOI:10.1109/MCOM.2003.1252803