A 2-nW 1.1-V self-biased current reference in CMOS technology

This work presents the design of an ultra-low-power self-biased 400-pA current source. We propose the use of a very simple topology along with a design methodology based on the concept of inversion level. An efficient design methodology has resulted in a cell area around 0.045 mm/sup 2/ in the AMI 1...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2005-02, Vol.52 (2), p.61-65
Main Authors: Camacho-Galeano, E.M., Galup-Montoro, C., Schneider, M.C.
Format: Article
Language:English
Subjects:
Analog integrated circuits
Circuits
CMOS
CMOS analog integrated circuit
CMOS technology
Control
current source
Current sources
Design engineering
Design methodology
Electric potential
Energy consumption
Low voltage
Methodology
Mirrors
MOSFET circuits
Paper technology
proportional to absolute temperature (PTAT) voltage
Temperature
Thermal resistance
Voltage
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Summary:This work presents the design of an ultra-low-power self-biased 400-pA current source. We propose the use of a very simple topology along with a design methodology based on the concept of inversion level. An efficient design methodology has resulted in a cell area around 0.045 mm/sup 2/ in the AMI 1.5-/spl mu/m CMOS technology and power consumption around 2 nW for 1.2-V supply. Simulated and experimental results validate the design and show that the current source can operate at supply voltages down to 1.1 V with a good regulation (
ISSN:1549-7747
1057-7130
1558-3791
DOI:10.1109/TCSII.2004.842059