Integrated floorplanning with buffer/channel insertion for bus-based designs

A new approach to the interconnect-driven floorplanning problem integrates bus planning and is intended for bus-based designs where each bus consists of a large number of wires. The floorplanner optimizes the timing and ensures routability by generating the exact location and shape of interconnects...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2003-06, Vol.22 (6), p.730-741
Main Authors: Rafiq, F., Chrzanowska-Jeske, M., Yang, H.H., Jeske, M., Sherwani, N.
Format: Article
Language:English
Subjects:
Application specific integrated circuits
Buses (vehicles)
Channels
Circuits
Computer aided design
Design engineering
Design optimization
Insertion
Integrated circuit interconnections
Iterative algorithms
Microelectronics
Microprocessors
Simulated annealing
Time measurements
Timing
Very large scale integration
Wire
Wires
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A new approach to the interconnect-driven floorplanning problem integrates bus planning and is intended for bus-based designs where each bus consists of a large number of wires. The floorplanner optimizes the timing and ensures routability by generating the exact location and shape of interconnects above and between the circuit blocks. Experiments with Microelectronics Center of North Carolina benchmarks clearly show the advantage of integrated floorplanning over the classical floorplan-analysis-and-then-refloorplan approach. Our floorplans are routable, meet all timing constraints, and are on average 12%-13% smaller in area as compared to traditional floorplanning algorithms.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2003.811443