High-performance arithmetic coding VLSI macro for the H264 video compression standard

This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a processor-coprocessor architecture to reduce it by more than an order of magnitude. The proposed coprocessor is based on an innovative algorithm known as the MZ-coder and main...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on consumer electronics 2005-02, Vol.51 (1), p.144-151
Main Authors: Nunez, J.L., Chouliaras, V.A.
Format: Article
Language:English
Subjects:
Algorithms
Architecture
Arithmetic
Arithmetic coding
Central Processing Unit
CMOS technology
Code standards
Coding
Computational efficiency
Coprocessors
Decoding
Electronics
Personal digital assistants
Very large scale integration
Video coding
Video compression
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a processor-coprocessor architecture to reduce it by more than an order of magnitude. The proposed coprocessor is based on an innovative algorithm known as the MZ-coder and maintains the original coding efficiency via a low-complexity, multiplication-free, non-stalling, fully pipelined architecture. The coprocessor achieves a constant throughput for both coding and decoding processes of 1 symbol per cycle and is designed to be attached to a controlling embedded RISC CPU whose instruction set has been extended with arithmetic coding instructions.
ISSN:0098-3063
1558-4127
DOI:10.1109/TCE.2005.1405712