Impact of flip-chip packaging on copper/low-k structures

• Published in: IEEE transactions on advanced packaging 2003-11, Vol.26 (4), p.433-440
• Main Authors: Mercado, L.L., Kuo, S.-M., Goldberg, C., Frear, D.
• Format: Article
• Language: English
• Subjects: AGING MECHANISMS; Applied sciences; Arrays; CHIPS; Copper; Delamination; Design. Technologies. Operation analysis. Testing; Driving; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Electronics packaging; Exact sciences and technology; Force measurement; FRACTURE MECHANICS; IMPACT PROPERTIES; Integrated circuit packaging; Integrated circuit reliability; INTEGRATED CIRCUITS; Materials reliability; MATHEMATICAL ANALYSIS; Mathematical models; Microassembly; Microelectronic fabrication (materials and surfaces technology); Packages; PACKAGING; RESIDUAL STRESS; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Surface mount technology; Testing, measurement, noise and reliability; Thermal expansion; THIN FILMS; Wafer scale integration
• ISSN: 1521-3323; 1557-9980
• DOI: 10.1109/TADVP.2003.821084

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.