A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit

A low-power 802.11abg SoC which achieves the best reported sensitivity as well as lowest reported power consumption and utilizes an extensive array of auto calibrations is reported. This SoC utilizes a two-antenna array receiver to build a single [abstract truncated by publisher].

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2008-05, Vol.43 (5), p.1101-1118
Main Authors: Afsahi, A, Rael, J J, Behzad, A, Chien, Hung-Ming, Pan, M, Au, S., Ojo, A, Lee, C P, Anand, S B, Chien, K, Wu, S., Roufoogaran, R, Zolfaghari, A, Leete, J C, Tran, Long, Carter, K A, Nariman, M, Yeung, K.W.-K., Morton, W
Format: Article
Language:English
Online Access:Get full text
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Description
Summary:A low-power 802.11abg SoC which achieves the best reported sensitivity as well as lowest reported power consumption and utilizes an extensive array of auto calibrations is reported. This SoC utilizes a two-antenna array receiver to build a single [abstract truncated by publisher].
ISSN:0018-9200
DOI:10.1109/JSSC.2008.920338