AsAP: An Asynchronous Array of Simple Processors

An array of simple programmable processors is implemented in 0.18 mum CMOS and contains 36 asynchronously clocked independent processors. Each processor occupies 0.66 and is fully functional at a clock rate of 520-540 MHz at 1.8 V and over 600 MHz at 2.0 V. Processors dissipate an average of 32 mW u...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2008-03, Vol.43 (3), p.695-705
Main Authors: Zhiyi Yu, Meeuwsen, M.J., Apperson, R.W., Sattari, O., Lai, M., Webb, J.W., Work, E.W., Truong, D., Mohsenin, T., Baas, B.M.
Format: Article
Language:English
Subjects:
Applied sciences
Array processor
Arrays
chip multi-processor
Circuit properties
Circuits
Clocks
CMOS
Computer architecture
Costs
Design. Technologies. Operation analysis. Testing
Digital signal processing
Digital signal processing chips
Dissipation
DSP
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Encoders
Energy efficiency
Exact sciences and technology
Fabrication
GALS
globally asynchronous locally synchronous
High performance computing
Image compression
Integrated circuits
Integrated circuits by function (including memories and processors)
many-core
MIMD
multi-core
Processors
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
Throughput
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Description
Summary:An array of simple programmable processors is implemented in 0.18 mum CMOS and contains 36 asynchronously clocked independent processors. Each processor occupies 0.66 and is fully functional at a clock rate of 520-540 MHz at 1.8 V and over 600 MHz at 2.0 V. Processors dissipate an average of 32 mW under typical conditions at 1.8 V and 475 MHz, and 2.4 mW at 0.9 V and 116 MHz while executing applications such as a JPEG encoder core and a fully compliant IEEE 802.11 a/g wireless LAN baseband transmitter.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2007.916616