Reliability Mechanisms of LTPS-TFT With [Formula Omitted] Gate Dielectric: PBTI, NBTI, and Hot-Carrier Stress

In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with gate dielectric is reported for the first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PB...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2008-05, Vol.55 (5), p.1153-1160
Main Authors: Ma, Ming-Wen, Chen, Chih-Yang, Wu, Woei-Cherng, Su, Chun-Jung, Kao, Kuo-Hsing, Chao, Tien-Sheng, Lei, Tan-Fu
Format: Article
Language:English
Subjects:
Density
Dielectrics
Gates
Grain boundaries
Instability
Niobium base alloys
Stability
Stresses
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Summary:In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with gate dielectric is reported for the first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PBS), positive-bias temperature instability (PBTI), negative-bias stress (NBS), negative-bias temperature instability (NBTI), and hot-carrier stress, are used to differentiate the distribution and mechanism of trap density states. The generation of deep-trap states of the effective interfacial layer (IL), tail-trap states of poly-Si grain boundaries, and electron trapping of the gate dielectric is observed for the PBS and PBTI of the LTPS-TFT. In addition, both the deep- and tail-trap states of the effective IL are generated under NBS and NBTI of the LTPS-TFT.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2008.919710