Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis

A processor architecture combining high-performance and low-power is presented. A prototype chip, Xetal-II, has been realized in 90 nm CMOS technology based on the proposed architecture. Recent experimental results show a compute performance of up to 140 GOPS at 785 mW when operating at 110 MHz. The...

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Bibliographic Details
Published in:Journal of signal processing systems 2011-01, Vol.62 (1), p.17-27
Main Authors: Abbo, Anteneh A., Kleihorst, Richard P., Schueler, Ben
Format: Article
Language:English
Subjects:
Architecture
Circuits and Systems
CMOS
Computational efficiency
Computer Imaging
Electrical Engineering
Engineering
Image Processing and Computer Vision
Kernels
Microprocessors
Pattern Recognition
Pattern Recognition and Graphics
Scene analysis
Signal processing
Signal,Image and Speech Processing
Vision
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Summary:A processor architecture combining high-performance and low-power is presented. A prototype chip, Xetal-II, has been realized in 90 nm CMOS technology based on the proposed architecture. Recent experimental results show a compute performance of up to 140 GOPS at 785 mW when operating at 110 MHz. The main architectural feature that allows high computational efficiency is the massively-parallel single-instruction multiple-data (MP-SIMD) compute paradigm. Due to the high data-level parallelism, applications like video scene analysis can efficiently exploit the proposed architecture. The chip has an internal 16-bit datapath and 10 Mbit of on-chip video memory facilitating energy efficient implementation of video processing kernels.
ISSN:1939-8018
1939-8115
DOI:10.1007/s11265-008-0332-1