Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI

We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region unde...

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Bibliographic Details
Published in:IEEE electron device letters 2002-03, Vol.23 (3), p.145-147
Main Authors: Mastrapasqua, M., Palestri, P., Pacelli, A., Celler, G.K., Frei, M.R., Smith, P.R., Johnson, R.W., Bizzarro, L., Lin, W., Ivanov, T.G., Carroll, M.S., Kizilyalli, I.C., King, C.A.
Format: Article
Language:English
Subjects:
BiCMOS integrated circuits
Capacitance
Cost engineering
Costs
Devices
Fabrication
Germanium silicon alloys
Heat transfer
Implants
Lithography
Oxides
Silicon germanides
Silicon germanium
Thermal conductivity
Thermal resistance
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Summary:We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.988819