10- and 40-Gb/s forward error correction devices for optical communications

• Published in: IEEE journal of solid-state circuits 2002-11, Vol.37 (11), p.1565-1573
• Main Authors: Leilei Song, Meng-Lin Yu, Shaffer, M.S.
• Format: Article
• Language: English
• Subjects: Channels; Counting; Decoders; Decoding; Devices; Error correction; Error correction & detection; Error correction codes; Forward error correction; Gates; High speed optical techniques; Monitoring; Optical devices; Optical fiber communication; Optical signal processing; Reed-Solomon codes; SONET; Studies; Throughput
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2002.803931

Two standard forward error correction (FEC) devices for 10- and 40-Gb/s optical systems are presented. The first FEC device includes RS(255, 239) FEC, BCH(4359, 4320) FEC, and standard compliant framing and performance monitoring functions. It can support a single 10-Gb/s channel or four asynchronous 2.5-Gb/s channels. The second FEC device implements RS(255, 239) FEC at a data rate of 40 Gb/s. This paper presents the key ideas applied to the design of Reed-Solomon (RS) decoder blocks in these devices, especially those for achieving high throughput and reducing complexity and power. Implemented in a 1.5-V, 0.16-/spl mu/m CMOS technology, the RS decoder in the 10-Gb/s, quad 2.5-Gb/s device has a core gate count of 424 K and consumes 343 mW; the 40-Gb/s RS decoder has a core gate count of 364 K and an estimated power consumption of 360 mW. The 40-Gb/s RS FEC is the highest throughput implementation reported to date.